Semiconductor Device Having Buried Word Line Interconnects and Method of Fabricating the Same

ABSTRACT

A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

RELATED APPLICATION

This application claims priority to Korean Patent Application No.2006-0080700, filed Aug. 24, 2006, the contents of which are herebyincorporated herein by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices, and moreparticularly, to semiconductor devices having buried word lines andmethods of fabricating the same.

BACKGROUND OF THE INVENTION

Integrated circuits include discrete devices, such as transistors, andinterconnects for electrically connecting the discrete devices to eachother. A typical transistor has a source region, a drain region and agate electrode, which are disposed on a semiconductor substrate. Thesource and drain regions are spaced apart from each other in an activeregion of the semiconductor substrate. The gate electrode is disposedbetween the source region and the drain region and insulated from theactive region.

Recently, as semiconductor devices have become more highly integrated,techniques have been developed that involve burying a gate electrode ina gate trench crossing the active region. A memory device, such as adynamic random access memory (DRAM), typically has a plurality of celltransistors disposed in a cell array region and p-channel metal oxidesemiconductor (pMOS) transistors and n-channel metal oxide semiconductor(nMOS) transistors disposed in a peripheral circuit region. The celltransistors are disposed at predetermined intervals in the cell arrayregion. Gate electrodes of the cell transistors are connected to a wordline.

A conventional technique for forming a buried word line involves buryingthe word line at a lower level than a top surface of the active region.For example, a semiconductor device having a buried word line isdisclosed in U.S. Pat. No. 6,770,535 B2 entitled to “SemiconductorIntegrated Circuit Device and Process for Manufacturing the Same” byYamada et al.

Planar transistors such as high-voltage transistors may be disposed inthe peripheral circuit region. Gate electrodes of the planar transistorsmay be disposed at a higher level than the active region. In addition, aplurality of gate lines may be formed at the same level as the gateelectrodes.

However, the buried word line typically must be electrically connectedto a gate line of the peripheral circuit region corresponding thereto. Atechnique for electrically connecting the buried word line with the gateline using a bypass interconnect and a contact plug has been developed.According to the technique using a bypass interconnect and a contactplug, a first interlayer insulating layer covering the buried word lineand the gate line is formed, the bypass interconnect is disposed on thefirst interlayer insulating layer, and the contact plug penetrating thefirst interlayer insulating layer is used.

Other interconnects crossing between the buried word line and the gateline may be disposed on the first interlayer insulating layer. In orderto electrically connect the buried word line with the gate line, asecond interlayer insulating layer is formed on the first interlayerinsulating layer, the bypass interconnect is disposed on the secondinterlayer insulating layer, and a contact plug penetrating the firstand second interlayer insulating layers is used. The contact plug maydifficult to form, and a signal transmission path may be lengthened.Consequently, a technique using a bypass interconnect and a contact plugmay not provide an advantageous structure for high integration, and maydegrade electrical characteristics and reliability.

SUMMARY OF THE INVENTION

In some embodiments of the present invention, a semiconductor deviceincludes a semiconductor substrate having a cell region and a peripheralcircuit region defined therein. A buried word line is disposed in thesubstrate in the cell region and has a top surface lower than topsurfaces of cell active regions in the cell region. A gate line isdisposed on the substrate in the peripheral circuit region. A unitaryword line interconnect is disposed in the substrate in the peripheralcircuit region, the word line interconnect including a first portioncontacting the buried word line and having a top surface lower than atop surfaces of the cell active regions and a second portion that isoverlapped by and in contact with the gate line.

The second portion of the word line interconnect may extend verticallyfrom the first portion of the word line interconnect to contact a bottomsurface of the gate line. The first portion of the word lineinterconnect may be laterally offset with respect to the buried wordline. The top surface of the first portion of the word line interconnectmay be at substantially the same level at the top surface of the buriedword line and the first portion of the word line interconnect may havesubstantially the same cross-sectional area as the buried word line. Aninsulating pattern may be disposed on the first portion of the word lineinterconnect and the buried word line. A bottom surface of theinsulating pattern may be lower than the top surfaces of the cell activeregions. A bit line may be disposed on the insulating pattern and maycross the buried word line.

In further embodiments, the semiconductor device may further includesecond and third spaced-apart gate lines on the substrate in theperipheral circuit region on respective sides of the bit line. A buriedperipheral circuit interconnect may be disposed in the substrate in theperipheral circuit region beneath the bit line, and may connect thefirst and second gate lines and have a portion beneath the bit line thathas a top surface at substantially the same level as the top surface ofthe buried word line.

Further embodiments of the present invention provide methods offabricating a semiconductor device. An isolation region is formed in asemiconductor substrate, defining cell active regions in a cell regionand peripheral circuit active regions in a peripheral circuit region. Aword line trench is formed in the substrate in the cell region and anadjoining word line interconnect trench is formed in the peripheralcircuit region. A word line pattern is formed in the word line trenchand a word line interconnect pattern is formed in the word lineinterconnect trench. A gate line is formed on the substrate in theperipheral circuit region, the gate line having an end portion thatoverlaps the word line interconnect pattern. The word line pattern andthe word line interconnect pattern are etched back to form a word linein the word line trench having a top surface lower than a top surface ofthe cell active regions and a word line interconnect in the word lineinterconnect trench having a first portion connected to the word lineand a top surface lower than the top surfaces of the cell active regionsand a second portion extending vertically from the first portion tocontact a bottom surface of the gate line. An insulating pattern isformed on the buried word line and the first portion of the word lineinterconnect.

In some embodiments, forming a word line trench includes forming a firstsacrificial mask pattern on the substrate having the isolation layer,forming sacrificial spacers on sidewalls of the first sacrificial maskpattern, forming a second sacrificial mask pattern filling a gap betweenthe sacrificial spacers, removing the sacrificial spacers and etchingthe isolation layer and the semiconductor substrate using the first andsecond sacrificial mask patterns as etching masks to form the word linetrench and the word line interconnect trench. Forming a firstsacrificial mask pattern on the substrate may be preceded by forming aperipheral circuit gate dielectric layer on the peripheral circuitactive regions, forming a peripheral circuit gate conductive layer onthe peripheral circuit gate dielectric layer and forming a sacrificialoxide layer on the peripheral circuit gate conductive layer. In someembodiments, forming a gate line includes etching the first and secondsacrificial mask patterns and the sacrificial oxide layer to expose theperipheral circuit gate conductive layer, forming a metal layer coveringthe peripheral circuit gate conductive layer, the word line pattern, andthe word line interconnect pattern and patterning the metal layer andthe peripheral circuit gate conductive layer to form the gate line. Theword line pattern and the word line interconnect pattern may be formedfrom a common metal layer.

In further embodiments, a bit line is formed on the insulating patternand crossing the buried word line. A peripheral circuit interconnecttrench may be formed in the substrate in the peripheral circuit regionconcurrent with forming the word line trench in the substrate in thecell region and the adjoining word line interconnect trench in theperipheral circuit region. A peripheral circuit interconnect pattern maybe formed in the peripheral circuit interconnect trench concurrent withforming the word line pattern in the word line trench and the word lineinterconnect pattern in the word line interconnect trench. Second andthird spaced apart gate lines may be formed in the peripheral circuitregion on respective sides of the bit line concurrent with forming thefirst gate line on the substrate in the peripheral circuit region, thefirst and second gate lines overlapping and contacting the peripheralcircuit interconnect pattern. The peripheral circuit interconnectpattern may be etched back concurrent with etching back the word linepattern and the word line interconnect pattern to form a peripheralcircuit interconnect having a first portion with a top surface that islower than a top surface of the peripheral circuit active regions andsecond portions that extend vertically from the first portion to contactbottom surfaces of respective ones of the second and third gate lines.An insulating pattern may be formed on the first portion of theperipheral circuit interconnect concurrent with forming the insulatingpattern on the buried word line and the first portion of the word lineinterconnect.

Some embodiments of the invention provides semiconductor devicesincluding interconnects that may be advantageous to high integration andmay have excellent electrical characteristics.

Other embodiments of the invention provide methods of fabricating asemiconductor device including interconnects that may be advantageous tohigh integration and may have excellent electrical characteristics.

In some embodiments, the present invention provides semiconductordevices having buried interconnects. A device has an isolation layerdisposed on a semiconductor substrate. By the isolation layer, cellactive regions are defined in a cell region, and peripheral circuitactive regions are defined in a peripheral circuit region. A buried wordline is disposed in the cell region. The buried word line is disposed ata lower level than the top surface of the cell active region. A buriedinterconnect is disposed in the peripheral circuit region. The buriedinterconnect is disposed at a lower level than the top surface of theperipheral circuit active regions. Gate lines are disposed at a higherlevel than the buried interconnect. The gate lines have regionsoverlapping the buried interconnect. In the overlapping regions, theburied interconnect contacts the gate lines.

In some embodiments of the present invention, the buried interconnectmay project toward the gate lines in the overlapping region.

In other embodiments, the gate line may project toward the buriedinterconnect in the overlapping region.

In still other embodiments, the buried interconnect may be disposed atthe same level as the buried word line. In addition, the buriedinterconnect may have the same cross-sectional area as the buried wordline. Furthermore, the buried interconnect may be the same materiallayer as the buried word line. In this case, the buried interconnect andthe buried word line may have a metal layer. The metal layer may be atitanium nitride (TiN) layer.

In yet other embodiments, the buried interconnect and the buried wordline may be in contact with each other.

In yet other embodiments, the buried interconnect may have twooverlapping regions spaced apart from each other. One of the gate linespassing through an n-channel metal oxide semiconductor (nMOS) region maycontact one part of the buried interconnect in one of the overlappingregions. The other one of the gate lines passing through a p-channelmetal oxide semiconductor (pMOS) region may contact the other part ofthe buried interconnect in the other of the overlapping regions.

In yet other embodiments, the gate lines may be disposed at a higherlevel than the peripheral circuit active regions.

In yet other embodiments, an insulating pattern may be disposed on theburied interconnect and buried word line. The bottom surface of theinsulating pattern may be disposed at a lower level than the topsurfaces of the adjacent active regions.

In yet other embodiments, a bit line crossing the buried interconnectmay be disposed on the insulating pattern.

In other embodiments, the present invention provides methods offabricating semiconductor devices. A method may include: providing asemiconductor substrate having a cell region and a peripheral circuitregion; forming an isolation layer defining cell active regions in thecell region and peripheral circuit active regions in the peripheralcircuit region; etching the cell active regions and the isolation layer,and simultaneously forming word line trenches in the cell region andinterconnect trenches in the peripheral circuit region; simultaneouslyforming word lines in the word line trenches and interconnect patternsin the interconnect trenches; forming gate lines on the semiconductorsubstrate having the interconnect patterns, the gate lines havingregions overlapping the interconnect patterns; etching-back the wordlines and the interconnect patterns and forming buried word lines andburied interconnects, the buried interconnects contacting the gate linesin the overlapping regions; and forming an insulating pattern on theburied word lines and the buried interconnects.

In some embodiments of the present invention, forming the word linetrenches and the interconnect trenches may include: forming a firstsacrificial mask pattern on the substrate having the isolation layer;forming sacrificial spacers on sidewalls of the first sacrificial maskpattern; forming a second sacrificial mask pattern filling a gap betweenthe sacrificial spacers; removing the sacrificial spacers; and etchingthe isolation layer and the cell active layers using the first andsecond sacrificial mask patterns as etching masks. The first and secondmask patterns may be formed of a material layer having an etchselectivity with respect to the active regions and the isolation layer.The sacrificial spacers may be formed of a polysilicon layer. The wordline trenches and the interconnect trenches may be formed to have asmaller width than the resolution limit of a photolithography process.

In other embodiments, before the first sacrificial mask pattern isformed, a peripheral circuit gate dielectric layer may be formed on theperipheral circuit active regions. A peripheral circuit gate conductivelayer may be formed on the semiconductor substrate having the peripheralcircuit gate dielectric layer. A sacrificial oxide layer may be formedon the peripheral circuit gate conductive layer.

In still other embodiments, forming the gate lines may include: whilethe word lines and the interconnect patterns are formed, etching thesacrificial mask patterns and the sacrificial oxide layer and exposingthe peripheral circuit gate conductive layer; forming a metal layercovering the peripheral circuit gate conductive layer, the word lines,and the interconnect patterns; and continuously patterning the metallayer and the peripheral circuit gate conductive layer.

In yet other embodiments, the word lines and the interconnect patternsmay be formed of a metal layer.

In yet other embodiments, the word line trenches may be formed to beconnected to the interconnect trenches corresponding thereto,respectively.

In yet other embodiments, the bottom surface of the insulating patternmay be formed at a lower level than the top surfaces of the adjacentactive regions.

In yet other embodiments, a bit line disposed on the insulating patternand crossing the buried interconnects may be formed.

In additional embodiments, the present invention provides additionalmethods of fabricating a semiconductor device. A method may include:providing a semiconductor substrate having a cell region and aperipheral circuit region; forming an isolation layer defining cellactive regions in the cell region and peripheral circuit active regionsin the peripheral circuit region; etching the cell active regions andthe isolation layer, and simultaneously forming word line trenches inthe cell region and interconnect trenches in the peripheral circuitregion; simultaneously forming buried word lines in the word linetrenches and buried interconnects in the interconnect trenches; forminggate lines on the semiconductor substrate having the buriedinterconnects, the gate lines having regions overlapping the buriedinterconnects, the buried interconnects contacting the gate lines in theoverlapping regions; and forming an insulating pattern on the buriedword lines and the buried interconnects disposed at a lower level thantop surfaces of the adjacent active regions.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of theinvention will be apparent from the more particular description ofexemplary embodiments of the invention, as illustrated in theaccompanying drawings. The drawings are not necessarily to scale,emphasis instead being placed upon illustrating the principles of theinvention.

FIG. 1 is a plan view of a semiconductor device having buriedinterconnects according to first exemplary embodiments of the presentinvention.

FIGS. 2 through 14 are composites of cross-sectional views illustratingoperations for forming the semiconductor device of FIG. 1.

FIG. 15 is a plan view of a semiconductor device having buriedinterconnects according to second exemplary embodiments of the presentinvention.

FIGS. 16 to 21 are composites of cross-sectional views illustratingoperations for forming the semiconductor device of FIG. 15.

FIG. 22 is a plan view of a semiconductor device having buriedinterconnects according to third exemplary embodiments of the presentinvention.

FIG. 23 is a composite of cross-sectional views illustrating operationsfor forming the semiconductor device of FIG. 23.

FIG. 24 is a plan view of a semiconductor device having buriedinterconnects according to fourth exemplary embodiments of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are illustrated. The invention may, however, beembodied in different forms and should not be construed as limited tothe embodiments set fourth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” and/or “coupled to” another element or layer,the element or layer may be directly on, connected and/or coupled to theother element or layer, or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon,” “directly connected to” and/or “directly coupled to” anotherelement or layer, no intervening elements or layers are present. As usedherein, the term “and/or” includes any and all combinations of one ormore of the associated listed items.

It will also be understood that, although the terms “first,” “second,”etc., may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. Rather,these terms are used merely as a convenience to distinguish one element,component, region, layer and/or section from another element, component,region, layer and/or section. For example, a first element, component,region, layer and/or section could be termed a second element,component, region, layer and/or section without departing from theteachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” “top,” “bottom” and the like, may be used to describe anelement and/or feature's relationship to another element(s) and/orfeature(s) as, for example, illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use and/or operation in additionto the orientation depicted in the figures. For example, when the devicein the figures is turned over, elements described as below and/orbeneath other elements or features would then be oriented above theother elements or features. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly. As used herein,“height” refers to a direction that is generally orthogonal to the facesof a substrate.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit of the invention. As usedherein, the singular terms “a,” “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprise,”“comprising,” “includes,” “including,” “have”, “having” and variantsthereof specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence and/or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Embodiments of the present invention may be described with reference tocross-sectional illustrations, which are schematic illustrations ofidealized embodiments of the present invention. As such, variations fromthe shapes of the illustrations, as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,embodiments of the present invention should not be construed as limitedto the particular shapes of regions illustrated herein, but are toinclude deviations in shapes that result from, e.g., manufacturing. Forexample, a region illustrated as a rectangle may have rounded or curvedfeatures. Thus, the regions illustrated in the figures are schematic innature and are not intended to limit the scope of the present invention.Like reference numerals refer to like elements throughout.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Semiconductor devices and methods of fabricating the same according tofirst exemplary embodiments of the present invention will now bedescribed with reference to FIGS. 1 to 14. FIG. 1 is a plan view of asemiconductor device. FIGS. 2 to 14 are composites of cross-sectionalviews illustrating methods of fabricating the semiconductor device ofFIG. 1, in which a cross-section 1 is taken along line I-I′ of FIG. 1, across-section 2 is taken along line II-II′ of FIG. 1, a cross-section 3is taken along line III-III′ of FIG. 1, and a cross-section 4 is takenalong line IV-IV′ of FIG. 1.

Referring to FIGS. 1 and 2, an isolation layer 55 defining activeregions 53, 54 and 54P may be formed on a semiconductor substrate 51.The isolation layer 55 may be formed by a trench isolation technique.The isolation layer 55 may be formed of an insulating layer, such as asilicon oxide layer.

The semiconductor substrate 51 may be a silicon wafer having aperipheral circuit region 10 and a cell region 20. The active regions53, 54 and 54P may include cell active regions 53, n-channel metal oxidesemiconductor (nMOS) peripheral circuit active regions 54, and ap-channel metal oxide semiconductor (pMOS) peripheral circuit activeregions 54P. In the cell region 20, the cell active regions 53 may bearranged at predetermined intervals in row and column directions. ThenMOS peripheral circuit active regions 54 and the pMOS peripheralcircuit active regions 54P may be disposed in the peripheral circuitregion 10.

Subsequently, a process of implanting well ions into the active regions53, 54 and 54P may be performed. The well-ion implantation process mayinclude a process of implanting p-type impurity ions and a process ofimplanting n-type impurity ions. For example, the process of implantingp-type impurity ions into the cell active regions 53 and the nMOSperipheral circuit active regions 54 may be performed, and also, theprocess of implanting n-type impurity ions into the pMOS peripheralcircuit active regions 54P may be performed. In this case, nMOStransistors may be formed in the cell active regions 53 and the nMOSperipheral circuit active regions 54, and pMOS transistors may be formedin the pMOS peripheral circuit active regions 54P. Referring to FIGS. 1and 3, a peripheral circuit gate dielectric layer 57 may be formed onthe active regions 53, 54 and 54P. A peripheral circuit gate conductivelayer 58, a sacrificial oxide layer 59, and a first sacrificial masklayer 61 may be sequentially stacked on the semiconductor substrate 51having the peripheral circuit gate dielectric layer 57.

The peripheral circuit gate dielectric layer 57 may be a silicon oxidelayer, a high-k dielectric layer, or a combination thereof. Theperipheral circuit gate dielectric layer 57 may be formed to cover thesurfaces of the active regions 53, 54 and 54P. The peripheral circuitgate conductive layer 58 may be a conductive layer, such as an undopedpolysilicon layer. The peripheral circuit gate conductive layer 58 maycover the top surface of the semiconductor substrate 51 having theperipheral circuit gate dielectric layer 57.

The sacrificial oxide layer 59 may be a silicon oxide layer, such as athermal oxide layer. The sacrificial oxide layer 59 may cover the topsurface of the peripheral circuit gate conductive layer 58.

The first sacrificial mask layer 61 may be a material layer having anetch selectivity with respect to the peripheral circuit gate conductivelayer 58, the active regions 53, 54 and 54P, and the isolation layer 55.The first sacrificial mask layer 61 may be a nitride layer such as asilicon nitride layer.

Referring to FIGS. 1 and 4, the first sacrificial mask layer 61 ispatterned to form a first sacrificial mask pattern 61′ having firstopenings 61P. The sacrificial oxide layer 59 may be exposed at thebottom of the first openings 61P.

The first openings 61P may be formed in a groove shape in a columndirection in the cell region 20. Also, the first openings 61P may beformed parallel to each other. In addition, the first openings 61P maybe formed to cross over the cell active regions 53. Furthermore, thefirst openings 61P may extend from the cell region 20 to the peripheralcircuit region 10.

The first openings 61P may be formed in the peripheral circuit region 10as well. In this case, the first openings 61P may be formed on theisolation layer 55. Referring to FIGS. 1 and 5, sacrificial spacers 65may be formed on sidewalls of the first sacrificial mask pattern 61′.The sacrificial spacers 65 may be formed from a material layer having anetch selectivity with respect to the first sacrificial mask pattern 61′.The sacrificial spacers 65 may be polysilicon.

For example, a polysilicon layer covering inner walls of the firstopenings 61P and the top surface of the first sacrificial mask pattern61′ may be formed. The polysilicon layer may be anisotropically etched,so that the sacrificial oxide layer 59 may be exposed. In this case, thepolysilicon layer may remain on the sidewalls of the first openings 61P.Here, the thickness of the sacrificial spacers 65 can be adjusted bycontrolling deposition conditions of the polysilicon layer. Thesacrificial spacers 65 may have a smaller thickness than the resolutionlimit of a photolithography process. Alternatively, the anisotropicetching process may be omitted.

Referring to FIGS. 1 and 6, a patterning process for separating asacrificial spacer 65 may be performed. Specifically, a photoresistpattern 67 may be formed on the semiconductor substrate 51 having thesacrificial spacers 65. One of the sacrificial spacers 65 is partiallyetched using the photoresist pattern 67 as an etching mask, so that asecond opening 67P exposing the sacrificial oxide layer 59 may beformed. The second opening 67P may be selectively formed at both ends ofa first one of the openings 61P. For example, the second opening 67P maybe formed to overlap both ends of the first openings 61P extending fromthe cell region 20 to the peripheral circuit region 10. Subsequently,the photoresist pattern 67 may be removed.

Referring to FIGS. 1 and 7, a second sacrificial mask pattern 69 fillinga gap between the sacrificial spacers 65 and the first and secondopenings 61P and 67P may be formed.

Specifically, a second sacrificial mask layer filling the first openings61P and the second openings 67P and covering the semiconductor substrate51 may be formed. The second sacrificial mask layer is planarized untilthe sacrificial spacer 65 is exposed, so that the second sacrificialmask pattern 69 may be formed. A chemical-mechanical polishing (CMP)process or etch back process may be used for planarization of the secondsacrificial mask layer.

Referring to FIGS. 1 and 8, the sacrificial spacers 65 may be removed.An isotropic etching having an etch selectivity between the sacrificialmask patterns 61′ and 69 and the sacrificial spacers 65 may be used toremove the sacrificial spacers 65. In other words, the isotropic etchingmay have a high etch rate with respect to the sacrificial spacers 65.Consequently, the sacrificial mask patterns 61′ and 69 may remain on thesemiconductor substrate 51.

Using the sacrificial mask patterns 61′ and 69 as etching masks, thesacrificial oxide layer 59, the peripheral circuit gate conductive layer58, the peripheral circuit gate dielectric layer 57, the isolation layer55, and the cell active regions 53 are anisotropically etched, so thatword line trenches 71 and interconnect trenches 72 may be formed. Theword line trenches 71 may be formed in the cell region 20, and theinterconnect trenches 72 may be formed in the peripheral circuit region10. The word line trenches 71 may be connected to the interconnecttrenches 72 corresponding thereto, respectively. In other words, theword line trenches 71 may extend to be connected to the interconnecttrenches 72.

Sizes of the word line trenches 71 and the interconnect trenches 72 maybe determined by the sacrificial spacer 65. When the sacrificial spacer65 has a smaller width than the resolution limit of a photolithographyprocess, the word line trenches 71 and the interconnect trenches 72 mayalso be formed to have a width smaller than the resolution limit of aphotolithography process.

Referring to FIGS. 1 and 9, the sacrificial mask patterns 61′ and 69 maybe removed. An isotropic etching process may be used to remove thesacrificial mask patterns 61′ and 69. A cell gate dielectric layer 77may be formed on inner walls of the word line trenches 71. The cell gatedielectric layer 77 may be formed of a silicon oxide layer, a high-kdielectric layer, or a combination thereof. The cell gate dielectriclayer 77 may be formed to uniformly cover surfaces of the cell activeregions 53 exposed to the word line trenches 71.

On the semiconductor substrate 51 having the cell gate dielectric layer77, a word conductive layer may be formed. The word conductive layer isplanarized, so that word lines 78 may be formed in the word linetrenches 71, and simultaneously, interconnect patterns 79 may be formedin the interconnect trenches 72. A CMP process or etch back process maybe used for planarization of the word conductive layer. Subsequently,the sacrificial oxide layer 59 is removed, so that the peripheralcircuit gate conductive layer 58 may be exposed.

The word lines 78 and the interconnect patterns 79 may be formed of ametal layer, such as a titanium nitride (TiN) layer. The peripheralcircuit gate conductive layer 58, the word lines 78, and theinterconnect patterns 79 may be exposed on substantially the same plane.In addition, the word lines 78 and the interconnect patterns 79 may beformed at a lower level than the top surface of the peripheral circuitgate conductive layer 58. Furthermore, the word lines 78 may contact theinterconnect patterns 79 corresponding thereto, respectively.

The sacrificial mask patterns 61′ and 69 may be removed after the wordlines 78 and the interconnect patterns 79 are formed.

Impurity ions may be implanted into the peripheral circuit gateconductive layer 58. For example, n-type impurity ions may be implantedinto the peripheral circuit gate conductive layer 58 in an nMOS region,and p-type impurity ions may be implanted into a peripheral circuit gateconductive layer 58P in a pMOS region. Referring to FIGS. 1 and 10, anupper conductive layer 81 covering the peripheral circuit gateconductive layers 58 and 58P, the word lines 78, and the interconnectpatterns 79 may be formed. The upper conductive layer 81 may be formedof a metal layer such as tungsten (W) or tungsten silicide (WSi). Theupper conductive layer 81 may contact the peripheral circuit gateconductive layers 58 and 58P, the word lines 78, and the interconnectpatterns 79.

Referring to FIGS. 1 and 11, a hard mask pattern 83 may be formed on theupper conductive layer 81. The hard mask pattern 83 may be formed of anitride layer, such as a silicon nitride layer.

The upper conductive layer 81 and the peripheral circuit gate conductivelayers 58 and 58P are etched back using the hard mask pattern 83 as anetching mask, so that gate lines 85, 87 and 88 may be formed. The gatelines 85, 87 and 88 may include first gate lines 85, second gate lines87, and third gate lines 88. Under the gate lines 85, 87 and 88,patterned peripheral circuit gate conductive layers 58′ and 58P′ mayremain. In addition, the gate lines 85, 87 and 88 may have regions CAoverlapping the interconnect patterns 79.

As the result, parts of the interconnect patterns 79, except for theoverlapped regions CA, and the word lines 78 may be exposed. The exposedinterconnect patterns 79 and the word lines 78 are etched back, so thatburied word line interconnects 79′ and buried word lines 78′ may beformed.

In contrast with conventional contacts using contact plugs to contactburied word lines, the word line interconnects 79′ have a unitarystructure including a first portion at the same level as the buried wordlines 78′ and a second portion 79E that extends vertically from thefirst portion to contact the gate lines 85, 87 and 88 in the overlappingregions CA. The buried word lines 78′ and first portions of the buriedinterconnects 79′ have top surfaces lower than the top surfaces of theadjacent active regions 53, 54 and 54P. In some embodiments, the wordline interconnect may be formed from a common conductive layer with theburied word line, such that some embodiments may be viewed as providinga direct or plugless connection of a buried word line to a gate line.

Upper word line trenches 71′ may be formed on the buried word lines 78′,and upper interconnect trenches 72′ may be formed on the buriedinterconnects 79′.

The buried word lines 78′ may contact respective ones of the buriedinterconnects 79′. In this case, the buried interconnects 79′ may be incontact with one of the first gate lines 85. The buried word lines 78′may be electrically connected with the first gate lines 85.

The second gate lines 87 may be formed to cross over the nMOS peripheralcircuit active regions 54. The peripheral circuit gate dielectric layer57 and the patterned peripheral circuit gate conductive layers 58′sequentially stacked between the nMOS peripheral circuit active regions54 and the second gate lines 87 may be conserved.

The third gate lines 88 may be formed to cross over the pMOS peripheralcircuit active regions 54P. The peripheral circuit gate dielectric layer57 and the patterned peripheral circuit gate conductive layers 58P′sequentially stacked between the pMOS peripheral circuit active regions54P and the third gate lines 88 may be conserved.

The buried interconnects 79′ may be formed between the second gate lines87 and the third gate lines 88. In this case, one end of the buriedinterconnects 79′ may overlap the second gate lines 87, and the otherend thereof may overlap the third gate lines 88. Respective ends of theburied interconnects 79′ may project toward the second and third gatelines 87 and 88, respectively.

Referring to FIGS. 1 and 12, low-concentration impurity regions 92 maybe formed in the nMOS peripheral circuit active regions 54 on respectivesides of the second gate lines 87. Spacers 91 may be formed on sidewallsof the patterned peripheral circuit gate conductive layers 58′ and thegate lines 85, 87 and 88. The spacers 91 may be formed of a siliconoxide layer, a silicon nitride layer, or a combination thereof. Sourceand drain regions 93, 94 and 95 may be formed in the active regions 53,54 and 54P.

Subsequently, a first interlayer insulating layer 97 may be formed onthe semiconductor substrate 51. The first interlayer insulating layer 97may be formed of a silicon oxide layer. The first interlayer insulatinglayer 97 is planarized, so that the hard mask pattern 83 may be exposed.A CMP process or etch back process may be used for planarization of thefirst interlayer insulating layer 97.

While the spacers 91 and the first interlayer insulating layer 97 areformed, an insulating pattern 91′ may be formed on the buried word lines78′ and the buried interconnects 79′. More specifically, while thespacers 91 are formed, the insulating pattern 91′ may be formed in theupper word line trenches 71′ and the upper interconnect trenches 72′.Alternatively, the upper word line trenches 71′ and the upperinterconnect trenches 72′ may be filled by the first interlayerinsulating layer 97. Referring to FIGS. 1 and 13, the first interlayerinsulating layer 97 is patterned, so that bit contact holes 101 and 102exposing the source and drain regions 93 and 94 may be formed. Bit plugs103 and 104 filling the bit contact holes 101 and 102 may be formed. Bitlines 105 and 106 contacting the bit plugs 103 and 104 may be formed onthe first interlayer insulating layer 97. The bit lines 105 and 106 andthe bit plugs 103 and 104 may be formed of a metal layer, a polysiliconlayer, or a combination thereof. The bit lines 105 and 106 may includefirst bit lines 105 formed in the cell region 20 and second bit lines106 formed in the peripheral circuit region 10.

Referring to FIGS. 1 and 14, a second interlayer insulating layer 110may be formed on the semiconductor substrate 51 having the bit lines 105and 106. The second interlayer insulating layer 110 may be a siliconoxide layer. Node contact holes 111 penetrating the second interlayerinsulating layer 110 and the first interlayer insulating layer 97 andexposing the source and drain regions 95 may be formed. Node plugs 113filling the node contact holes 111 may be formed. Storage nodes 115contacting the node plugs 113 may be formed on the second interlayerinsulating layer 110. The storage nodes 115 and the node plugs 113 maybe a metal layer, a polysilicon layer, or a combination thereof.

Now, referring to FIGS. 1 and 14, a semiconductor device according tofirst exemplary embodiments of the present invention will be described.The device may have an isolation layer 55 disposed on a semiconductorsubstrate 51. The semiconductor substrate 51 may be a silicon waferhaving a peripheral circuit region 10 and a cell region 20.

By the isolation layer 55, cell active regions 53 may be defined in thecell region 20, and peripheral circuit active regions 54 and 54P may bedefined in the peripheral circuit region 10. The cell active regions 53may be arranged at predetermined intervals in row and column directionsin the cell region 20. The peripheral circuit active regions 54 and 54Pmay include nMOS peripheral circuit active regions 54 and pMOSperipheral circuit active regions 54P. The isolation layer 55 may be aninsulating layer such as a silicon oxide layer.

Buried word lines 78′ may be disposed in the cell region 20. The buriedword lines 78′ may be disposed at a lower level than the top surface ofthe cell active regions 53. Buried interconnects 79′ may be disposed inthe peripheral circuit region 10. The buried interconnects 79′ may bedisposed at a lower level than the top surface of the peripheral circuitactive regions 54 and 54 p.

Bottoms and sidewalls of the buried interconnects 79′ and the buriedword lines 78′ may be surrounded by a cell gate dielectric layer 77.Thus, the cell gate dielectric layer 77 may be interposed between theburied word lines 78′ and the cell active regions 53. The cell gatedielectric layer 77 may be a silicon oxide layer, a high-k dielectriclayer, or a combination thereof.

The buried interconnects 79′ may be disposed at the same level as theburied word lines 78′. In other words, bottom surfaces of the buriedinterconnects 79′ and the buried word lines 78′ may be disposed on thesame plane. In addition, the buried interconnects 79′ may have the samecross-sectional area as the buried word lines 78′. The buriedinterconnects 79′ and the buried word lines 78′ may have a smaller widththan the resolution limit of a photolithography process. Furthermore,the buried interconnects 79′ may be the same material layer as theburied word lines 78′. In this case, the buried interconnects 79′ andthe buried word lines 78′ may have a metal layer. The metal layer may bea titanium nitride (TiN) layer.

The gate lines 85, 87 and 88 may be disposed at a higher level than theburied interconnects 79′. A hard mask pattern 83 may be provided on thegate lines 85, 87 and 88. The hard mask pattern 83 may be a nitridelayer such as a silicon nitride layer.

The gate lines 85, 87 and 88 may include first gate lines 85, secondgate lines 87, and third gate lines 88. The gate lines 85, 87 and 88 maybe a metal layer such as a tungsten (W) layer or a tungsten silicide(WSi) layer. The gate lines 85, 87 and 88 may be disposed at a higherlevel than the peripheral circuit active regions 54 and 54P.

The gate lines 85, 87 and 88 may have overlapping regions CA overlappingthe buried interconnects 79′. In the overlapping regions CA, the buriedinterconnects 79′ may contact the gate lines 85, 87 and 88. The buriedinterconnects 79′ may project toward the gate lines 85, 87 and 88 in theoverlapping regions CA. In other words, the buried interconnects 79′ mayhave projections 79E projecting upward.

The buried word lines 78′ may contact the buried interconnects 79′corresponding thereto, respectively. In this case, the buriedinterconnects 79′ may be in contact with one of the first gate lines 85.In other words, the overlapping regions CA may be provided between theburied interconnects 79′ and the first gate lines 85. In the overlappingregions CA, the buried interconnects 79′ may have the projections 79Eprojecting toward the first gate lines 85. Consequently, the buried wordlines 78′ may be electrically connected with the first gate lines 85.

The second gate lines 87 may be disposed to cross over the nMOSperipheral circuit active regions 54. The third gate lines 88 may bedisposed to cross over the pMOS peripheral circuit active regions 54P.The buried interconnects 79′ may be disposed between the second gatelines 87 and the third gate lines 88. In this case, one end of theburied interconnects 79′ may overlap the second gate lines 87, and theother end thereof may overlap the third gate lines 88. In other words,the projections 79E projecting toward the second and third gate lines 87and 88 may be provided at the both ends of the buried interconnects 79′.

A peripheral circuit gate dielectric layer 57 and patterned peripheralcircuit gate conductive layers 58′ may be sequentially stacked betweenthe nMOS peripheral circuit active regions 54 and the second gate lines87. The peripheral circuit gate dielectric layer 57 may be a siliconoxide layer, a high-k dielectric layer, or a combination thereof. Thepatterned peripheral circuit gate conductive layers 58′ may be apolysilicon layer.

Between the pMOS peripheral circuit active regions 54P and the thirdgate line 88, the peripheral circuit gate dielectric layer 57 and thepatterned peripheral circuit gate conductive layers 58P′ may besequentially stacked. Also, between the isolation layer 55 and the gatelines 85, 87 and 88, the peripheral circuit gate dielectric layer 57 andthe patterned peripheral circuit gate conductive layers 58′ and 58P′ maybe sequentially stacked.

Spacers 91 may be disposed on sidewalls of the patterned peripheralcircuit gate conductive layers 58′ and the second gate lines 87. Thespacers 91 may be a silicon oxide layer, a silicon nitride layer, asilicon oxynitride layer, or a combination thereof.

Low-concentration impurity regions 92 may be disposed in the nMOSperipheral circuit active regions 54 under the spacers 91. Source anddrain regions 93, 94 and 95 may be disposed in the active regions 53, 54and 54P adjacent to both sides of the buried word lines 78′ and the gatelines 87 and 88.

An insulating pattern 91′ may be disposed on the buried interconnects79′ and the buried word lines 78′. The bottom surface of the insulatingpattern 91′ may be disposed at a lower level than the top surfaces ofthe adjacent active regions 53, 54 and 54P. The insulating pattern 91′may be a silicon oxide layer, a silicon nitride layer, a siliconoxynitride layer, or a combination thereof.

A first interlayer insulating layer 97 may be provided on thesemiconductor substrate 51 having the insulating pattern 91′. The firstinterlayer insulating layer 97 may be an insulating layer such as asilicon oxide layer.

Bit lines 105 and 106 may be disposed on the first interlayer insulatinglayer 97. The bit lines 105 and 106 may cross over the buriedinterconnects 79′ and the buried word lines 78′. The bit lines 105 and106 may include first bit lines 105 disposed in the cell region 20 andsecond bit lines 106 disposed in the peripheral circuit region 10. Thebit lines 105 and 106 may be connected to the source and drain regions93 and 94 through bit plugs 103 and 104 penetrating the first interlayerinsulating layer 97. The bit lines 105 and 106 and the bit plugs 103 and104 may be a metal layer, a polysilicon layer, or a combination thereof.

The semiconductor substrate 51 having the bit lines 105 and 106 may becovered by a second interlayer insulating layer 110. The secondinterlayer insulating layer 110 may be an insulating layer, such as asilicon oxide layer. Storage nodes 115 may be disposed on the secondinterlayer insulating layer 110. The storage nodes 115 may be connectedto the source and drain regions 95 through node plugs 113 sequentiallypenetrating the second interlayer insulating layer 110 and the firstinterlayer insulating layer 97. The storage nodes 115 and the node plugs113 may be a metal layer, a polysilicon layer, or a combination thereof.

As described above, according to the first embodiments of the presentinvention, the buried interconnects 79′ may be disposed at a lower levelthan the top surfaces of the active regions 53, 54 and 54P. Thus,arrangement of the bit lines 105 and 106 disposed on the insulatingpattern 91′ is not disturbed. In addition, a signal transmission pathcan be shortened in comparison with a conventional bypass interconnectmethod using a bit line layer or a metal interconnect layer.Consequently, a semiconductor device having excellent electricalcharacteristics and advantageous to high integration can be embodied.

A semiconductor device having buried interconnects and methods offabrication therefor according to second exemplary embodiments of thepresent invention will now be described with reference to FIGS. 15 to21. FIG. 15 is a plan view of a semiconductor device having buriedinterconnects according to the second exemplary embodiments of thepresent invention. FIGS. 16 to 21 are composites of cross-sectionalviews illustrating operations for fabricating the semiconductor deviceof FIG. 15, in which a cross-section 5 is taken along line V-V′ of FIG.15, a cross-section 6 is taken along line VI-VI′ of FIG. 15, and across-section 7 is taken along line VII-VII′ of FIG. 15.

Referring to FIGS. 15 and 16, an isolation layer 155 defining activeregions 153 and 153P in a peripheral circuit region may be formed in asemiconductor substrate 151. The semiconductor substrate 151 may be asilicon wafer having an nMOS region 10N and a pMOS region 10P. Theactive regions 153 and 153P may include nMOS peripheral circuit activeregions 153 and pMOS peripheral circuit active regions 153P. The nMOSperipheral circuit active regions 153 may be arranged in the nMOS region10N, and the pMOS peripheral circuit active regions 153P may be arrangedin the pMOS region 10P.

A peripheral circuit gate dielectric layer 157 may be formed on theactive regions 153 and 153P. A peripheral circuit gate conductive layer158 and a sacrificial oxide layer 159 may be sequentially stacked on thesemiconductor substrate 151 having the peripheral circuit gatedielectric layer 157.

A first sacrificial mask pattern 161 may be formed on the peripheralcircuit gate conductive layer 158. The first sacrificial mask pattern161 may be formed of a material layer having an etch selectivity withrespect to the peripheral circuit gate conductive layer 158, the activeregions 153 and 153P, and the isolation layer 155. A sacrificial spacer165 may be formed on sidewalls of the first sacrificial mask pattern161. The sacrificial spacer 165 may be formed of a material layer havingan etch selectivity with respect to the first sacrificial mask pattern161. The sacrificial spacer 165 may be formed of a polysilicon layer.The sacrificial spacer 165 may be formed to have a smaller thicknessthan the resolution limit of a photolithography process. Subsequently, apatterning process for separating the sacrificial spacer 165 may beperformed. Specifically, a photoresist pattern 167 may be formed on thesemiconductor substrate 151 having the sacrificial spacer 165. Thephotoresist pattern 167 may have a first opening 167P partially exposingthe sacrificial spacer 165.

Referring to FIGS. 15 and 17, the sacrificial spacer 165 is etched usingthe photoresist pattern 167 as an etching mask, so that a second opening165P exposing the sacrificial oxide layer 159 may be formed. The secondopening 165P may be selectively formed at both ends of the sacrificialspacer 165. Subsequently, the photoresist pattern 167 may be removed.

Referring to FIGS. 15 and 18, a second sacrificial mask pattern 169filling a gap between the sacrificial spacers 165 and the second opening165P may be formed. Referring to FIGS. 15 and 19, the sacrificial spacer165 may be removed. An isotropic etching having an etch selectivitybetween the sacrificial mask patterns 161 and 169 and the sacrificialspacer 165 may be used for removal of the sacrificial spacer 165.Consequently, the sacrificial mask patterns 161 and 169 may remain onthe semiconductor substrate 151.

The sacrificial oxide layer 159, the peripheral circuit gate conductivelayer 158, the peripheral circuit gate dielectric layer 157, and theisolation layer 155 are anisotropically etched using the sacrificialmask patterns 161 and 169 as etching masks, so that interconnecttrenches 172 may be formed.

The size of the interconnect trenches 172 may be determined by thesacrificial spacer 165. When the sacrificial spacer 165 has a smallerwidth than the resolution limit of a photolithography process, theinterconnect trenches 172 may also be formed to have a smaller widththan the resolution limit of a photolithography process.

Referring to FIGS. 15 and 20, the sacrificial mask patterns 161 and 169may be removed. A cell gate dielectric layer 177 may be formed on aninner wall of the interconnect trenches 172. Subsequently, interconnectpatterns 179 are formed in the interconnect trenches 172. Thesacrificial oxide layer 159 is removed, so that the peripheral circuitgate conductive layer 158 may be exposed.

The peripheral circuit gate conductive layer 158 and the interconnectpatterns 179 may be exposed on substantially the same plane. Inaddition, the interconnect patterns 179 may be formed at a lower levelthan the top surface of the peripheral circuit gate conductive layer158.

Alternatively, the sacrificial mask patterns 161 and 169 may be removedafter the cell gate dielectric layer 177 and the interconnect patterns179 are formed. Subsequently, impurity ions may be implanted into theperipheral circuit gate conductive layer 158. For example, n-typeimpurity ions may be implanted into the peripheral circuit gateconductive layer 158 in the nMOS region, and p-type impurity ions may beimplanted into a peripheral circuit gate conductive layer 158P in thepMOS region.

An upper conductive layer 181 covering the peripheral circuit gateconductive layers 158 and 158P and the interconnect patterns 179 may beformed. A hard mask pattern 183 may be formed on the upper conductivelayer 181.

Referring to FIGS. 15 and 21, the upper conductive layer 181 and theperipheral circuit gate conductive layers 158 and 158P are etched usingthe hard mask pattern 183 as an etching mask, so that gate lines 187 and188 may be formed. The gate lines 187 and 188 may include first gatelines 187 and second gate lines 188. The first gate lines 187 may bearranged in the nMOS region 10N, and the second gate lines 188 may bearranged in the pMOS region 10P.

Patterned peripheral circuit gate conductive layers 158′ and 158P′ mayremain under the gate lines 187 and 188. In addition, the gate lines 187and 188 may have regions CA overlapping the interconnect patterns 179.

As a result, parts of the interconnect patterns 179 except for theoverlapping regions CA may be exposed. The exposed interconnect patterns179 are etched back, so that buried interconnects 179′ may be formed.The buried interconnects 179′ may be formed at a lower level than thetop surfaces of the adjacent active regions 153 and 153P.

In the overlapping regions CA, the interconnect patterns 179 may beconserved under the gate lines 187 and 188. In this case, the buriedinterconnects 179′ may have projections 179E projecting upward. In otherwords, the buried interconnects 179′ may project toward the gate lines187 and 188 in the overlapping regions CA. Thus, the buriedinterconnects 179′ may contact the gate lines 187 and 188.

The first gate lines 187 may be formed to cross over the nMOS peripheralcircuit active regions 153. The peripheral circuit gate dielectric layer157 and the patterned peripheral circuit gate conductive layers 158′sequentially stacked between the nMOS peripheral circuit active regions153 and the first gate lines 187 may be conserved.

The second gate lines 188 may be formed to cross over the pMOSperipheral circuit active regions 153P. The peripheral circuit gatedielectric layer 157 and the patterned peripheral circuit gateconductive layers 158P′ sequentially stacked between the pMOS peripheralcircuit active regions 153P and the second gate lines 188 may beconserved.

The buried interconnects 179′ may be formed between the first gate lines187 and the second gate lines 188. In this case, one end of the buriedinterconnects 179′ may overlap the first gate lines 187, and the otherend thereof may overlap the second gate lines 188. The ends of theburied interconnects 179′ may project toward the first and second gatelines 187 and 188, respectively.

An insulating pattern 197 may be formed on the buried interconnects179′. The insulating pattern 197 may be formed of a silicon oxide layer,a silicon nitride layer, a silicon oxynitride layer, or a combinationthereof. Consequently, the semiconductor substrate 151 may be covered bythe hard mask pattern 183 and the insulating pattern 197.

As described above, the first gate lines 187 may be disposed in the nMOSregion 10N, and the second gate lines 188 may be disposed in the pMOSregion 10P. The first gate lines 187 may be electrically connected withthe second gate lines 188 by the buried interconnects 179′.

Now, a semiconductor device having buried interconnects and method offabricating the same according to third exemplary embodiments of thepresent invention will be described with reference to FIGS. 22 and 23.FIG. 22 is a plan view of a semiconductor device having buriedinterconnects according to the third exemplary embodiments of thepresent invention. FIG. 23 is a composite of cross-sectional viewsillustrating operations for fabricating the semiconductor device of FIG.22, in which a cross-section 8 is taken along line VIII-VIII′ of FIG.22, and a cross-section 9 is taken along line IX-IX′ of FIG. 22.

Referring to FIGS. 22 and 23, the patterning process for separating thesacrificial spacer (165 of FIG. 17) as described with reference to FIGS.16 and 17 is omitted in the method of fabricating a semiconductor deviceaccording to the third exemplary embodiments of the present invention.More specifically, the second opening (165P of FIG. 17) formed at bothends of the sacrificial spacer (165 of FIG. 17) is not formed.

Consequently, a semiconductor substrate according to the third exemplaryembodiments of the present invention may have an isolation layer 255disposed on a semiconductor substrate 251. The semiconductor substrate251 may be a silicon wafer having an nMOS region 10N and a pMOS region10P. By the isolation layer 255, nMOS peripheral circuit active regions253 may be defined in the nMOS region 10N, and pMOS peripheral circuitactive regions 253P may be defined in the pMOS region 10P.

Buried interconnects 279 may be disposed in interconnect trenches formedin the isolation layer 255. The buried interconnects 279 may be disposedat a lower level than the top surface of the peripheral circuit activeregions 253 and 253P. The bottom and sidewalls of the buriedinterconnects 279 may be surrounded by a cell gate dielectric layer 277.Gate lines 287 and 288 may be disposed at a higher level than the buriedinterconnects 279. A hard mask pattern 283 may be provided on the gatelines 287 and 288. The gate lines 287 and 288 may include first gatelines 287 and second gate lines 288. The gate lines 287 and 288 may bedisposed at a higher level than the peripheral circuit active regions253 and 253P.

The gate lines 287 and 288 may have regions CA overlapping the buriedinterconnects 279. In the overlapping regions CA, the buriedinterconnects 279 may contact the gate lines 287 and 288. The buriedinterconnects 279 may project toward the gate lines 287 and 288 in theoverlapping regions CA. In other words, the buried interconnects 279 mayhave projections 279E projecting upward.

The first gate lines 287 may be disposed to cross over the nMOSperipheral circuit active regions 253. The second gate lines 288 may bedisposed to cross over the pMOS peripheral circuit active regions 253P.A pair of the buried interconnects 279 may be disposed between the firstgate lines 287 and the second gate lines 288. In this case, one end ofthe buried interconnects 279 may overlap the first gate lines 287, andthe other end thereof may overlap the second gate lines 288. Inaddition, one pair of the buried interconnects 279 parallel to eachother may be in contact with each other in the overlapping regions CA.

A peripheral circuit gate dielectric layer 257 and patterned peripheralcircuit gate conductive layers 258 may be sequentially stacked betweenthe nMOS peripheral circuit active regions 253 and the first gate lines287.

The peripheral circuit gate dielectric layer 257 and patternedperipheral circuit gate conductive layers 258P may be sequentiallystacked between the pMOS peripheral circuit active regions 253P and thesecond gate lines 288. Also, the peripheral circuit gate dielectriclayer 257 and the patterned peripheral circuit gate conductive layers258 and 258P may be sequentially stacked between the isolation layer 255and the gate lines 287 and 288.

An insulating pattern 297 may be disposed on the buried interconnects279. The bottom surface of the insulating pattern 297 may be disposed ata lower level than the top surfaces of the adjacent active regions 253and 253P. Consequently, the semiconductor substrate 251 may be coveredby the hard mask pattern 283 and the insulating pattern 297.

As described above, the first gate lines 287 may be disposed in the nMOSregion 10N, and the second gate lines 288 may be disposed in the pMOSregion 10P. The first gate lines 287 may be electrically connected withthe second gate lines 288 by one pair of the buried interconnects 279.

Now, a semiconductor device having buried interconnects and methods offabricating the same according to fourth exemplary embodiments of thepresent invention will be described with reference to FIG. 24. In themethods of fabricating a semiconductor device according to the fourthexemplary embodiments of the present invention, a buried interconnect379 is formed, and then gate lines 387 and 388 are formed.

The semiconductor device according to the fourth exemplary embodimentsof the present invention may have an isolation layer 355 disposed on asemiconductor substrate 351. The semiconductor substrate 351 may be asilicon wafer having an nMOS region and a pMOS region. By the isolationlayer 355, an nMOS peripheral circuit active region 353 may be definedin the nMOS region, and a pMOS peripheral circuit active regions 353Pmay be defined in the pMOS region. The buried interconnect 379 may bedisposed in an interconnect trench formed in the isolation layer 355.The buried interconnect 379 may be disposed at a lower level than thetop surfaces of the peripheral circuit active regions 353 and 353P. Thebottom and sidewalls of the buried interconnect 379 may be surrounded bya cell gate dielectric layer 377. The gate lines 387 and 388 may bedisposed at a higher level than the buried interconnect 379. A hard maskpattern 383 may be provided on the gate lines 387 and 388. The gatelines 387 and 388 may include a first gate line 387 and a second gateline 388. The gate lines 387 and 388 may be disposed at a higher levelthan the peripheral circuit active regions 353 and 353P.

The gate lines 387 and 388 may have regions CA overlapping the buriedinterconnect 379. In the overlapping regions CA, the buried interconnect379 may contact the gate lines 387 and 388. The gate lines 387 and 388may project toward the buried interconnect 379 in the overlappingregions CA. In other words, projections 387E and 388E projectingdownward may be provided to the gate lines 387 and 388.

The first gate line 387 may be disposed cross over the nMOS peripheralcircuit active regions 353, and the second gate line 388 may be disposedcross over the pMOS peripheral circuit active regions 353P. The buriedinterconnect 379 may be disposed between the first gate line 387 and thesecond gate line 388. In this case, one end of the buried interconnect379 may overlap the first gate line 387, and the other end thereof mayoverlap the second gate line 388.

A peripheral circuit gate dielectric layer 357 and patterned peripheralcircuit gate conductive layers 358 may be sequentially stacked betweenthe nMOS peripheral circuit active regions 353 and the first gate line387. The peripheral circuit gate dielectric layer 357 and a patternedperipheral circuit gate conductive layer 358P may be sequentiallystacked between the pMOS peripheral circuit active regions 353P and thesecond gate line 388. Also, the peripheral circuit gate dielectric layer357 and the patterned peripheral circuit gate conductive layers 358 and358P may be sequentially stacked between the isolation layer 355 and thegate lines 387 and 388.

An insulating pattern 397 may be disposed on the buried interconnect379. The bottom surface of the insulating pattern 397 may be disposed ata lower level than the top surfaces of the adjacent active regions 353and 353P. Consequently, the semiconductor substrate 351 may be coveredby the hard mask pattern 383 and the insulating pattern 397.

As described above, according to some embodiments of the presentinvention, a buried word line is formed in a cell region while a buriedinterconnect is formed in a peripheral circuit region. The buriedinterconnect and the buried word line may be formed at a lower levelthan the top surface of an adjacent active region. Gate lines aredisposed at a higher level than the buried interconnect. The gate lineshave regions overlapping the buried interconnect. In the overlappingregions, the buried interconnect contacts the gate lines. An insulatingpattern is provided on the buried interconnect and the buried word line.One of the gate lines may be electrically connected to the other gateline or the buried word line through the buried interconnect. Therefore,a signal transmission path can be shortened in comparison with aconventional interconnect method.

In addition, bit lines may be disposed on the insulating pattern. Inthis case, the buried interconnect is provided under the insulatingpattern and thus does not disturb arrangement of the bit lines.

Consequently, it is possible to provide a semiconductor device havingexcellent electrical characteristics and advantageous to highintegration.

The foregoing is illustrative of the present invention and is not to beconstrued as limiting thereof. Although a few embodiments of thisinvention have been described, those skilled in the art will readilyappreciate that many modifications are possible in the embodimentswithout materially departing from the novel teachings and advantages ofthis invention. Accordingly, all such modifications are intended to beincluded within the scope of this invention as defined in the claims.The invention is defined by the following claims.

1. A semiconductor device comprising: a semiconductor substrate having acell region and a peripheral circuit region defined therein; a buriedword line in the substrate in the cell region and having a top surfacelower than top surfaces of cell active regions in the cell region; agate line on the substrate in the peripheral circuit region; and aunitary word line interconnect in the substrate in the peripheralcircuit region, the word line interconnect comprising a first portioncontacting the buried word line and having a top surface lower than topsurfaces of the cell active regions and a second portion that isoverlapped by and in contact with the gate line.
 2. The semiconductordevice of claim 1, wherein the second portion of the word lineinterconnect extends vertically from the first portion of the word lineinterconnect to contact a bottom surface of the gate line.
 3. Thesemiconductor device of claim 1, wherein the top surface of the firstportion of the word line interconnect is at substantially the same levelas the top surface of the buried word line.
 4. The semiconductor deviceof claim 1, wherein the first portion of the word line interconnect hassubstantially the same cross-sectional area as the buried word line. 5.The semiconductor device of claim 1, wherein the word line interconnectand the buried word line comprise a common metal layer.
 6. Thesemiconductor device of claim 1, wherein the gate line has a top surfacethat is higher than top surfaces of peripheral circuit active regions inthe peripheral circuit region.
 7. The semiconductor device of claim 1,further comprising an insulating pattern disposed on the first portionof the word line interconnect and the buried word line.
 8. Thesemiconductor device of claim 7, wherein a bottom surface of theinsulating pattern is lower than the top surfaces of the cell activeregions.
 9. The semiconductor device of claim 7, further comprising abit line disposed on the insulating pattern and crossing the buried wordline.
 10. The semiconductor device of claim 9, further comprising: firstand second spaced-apart gate lines on the substrate in the peripheralcircuit region on respective sides of the bit line; a buried peripheralcircuit interconnect in the substrate in the peripheral circuit regionbeneath the bit line, the buried peripheral circuit interconnectconnecting the first and second gate lines and having a portion beneaththe bit line that has a top surface at substantially the same level asthe top surface of the buried word line.
 11. The semiconductor device ofclaim 1, wherein the first portion of the word line interconnect islaterally offset with respect to the buried word line.
 12. A method offabricating a semiconductor device, comprising: forming an isolationregion in a semiconductor substrate, the isolation region defining cellactive regions in a cell region and peripheral circuit active regions ina peripheral circuit region; forming a word line trench in the substratein the cell region and an adjoining word line interconnect trench in theperipheral circuit region; forming a word line pattern in the word linetrench and a word line interconnect pattern in the word lineinterconnect trench; forming a gate line on the substrate in theperipheral circuit region, the gate line having an end portion thatoverlaps the word line interconnect pattern; etching back the word linepattern and the word line interconnect pattern to form word line in theword line trench having a top surface lower than top surfaces of thecell active regions and a word line interconnect in the word lineinterconnecting trench having a first portion connected to the word lineand a top surface lower than the top surfaces of the cell active regionsand a second portion extending vertically from the first portion tocontact a bottom surface of the gate line; and forming an insulatingpattern on the buried word line and the first portion of the word lineinterconnect.
 13. The method of claim 12, wherein forming a word linetrench in the cell region and an adjoining word line interconnect trenchin the peripheral circuit region comprises: forming a first sacrificialmask pattern on the substrate having the isolation layer; formingsacrificial spacers on sidewalls of the first sacrificial mask pattern;forming a second sacrificial mask pattern filling a gap between thesacrificial spacers; removing the sacrificial spacers; and etching theisolation layer and the semiconductor substrate using the first andsecond sacrificial mask patterns as etching masks to form the word linetrench and the word line interconnect trench.
 14. The method of claim13, wherein forming a first sacrificial mask pattern on the substratehaving the isolation layer is preceded by: forming a peripheral circuitgate dielectric layer on the peripheral circuit active regions; forminga peripheral circuit gate conductive layer on the peripheral circuitgate dielectric layer; and forming a sacrificial oxide layer on theperipheral circuit gate conductive layer.
 15. The method of claim 14,wherein forming a gate line comprises: etching the first and secondsacrificial mask patterns and the sacrificial oxide layer to expose theperipheral circuit gate conductive layer; forming a metal layer coveringthe peripheral circuit gate conductive layer, the word line pattern, andthe word line interconnect pattern; and patterning the metal layer andthe peripheral circuit gate conductive layer to form the gate line. 16.The method of claim 12, wherein the word line pattern and the word lineinterconnect pattern are formed from a common metal layer.
 17. Themethod of claim 12, wherein a bottom surface of the insulating patternis lower than top surfaces of the cell active regions.
 18. The method ofclaim 12, further comprising forming a bit line on the insulatingpattern and crossing the buried word line.
 19. The method of claim 18,further comprising: forming a peripheral circuit interconnect trench inthe substrate in the peripheral circuit region concurrent with formingthe word line trench in the substrate in the cell region and theadjoining word line interconnect trench in the peripheral circuitregion; forming a peripheral circuit interconnect pattern in theperipheral circuit interconnect trench concurrent with forming the wordline pattern in the word line trench and the word line interconnectpattern in the word line interconnect trench; forming second and thirdspaced apart gate lines in the peripheral circuit region on respectivesides of the bit line concurrent with forming the first gate line on thesubstrate in the peripheral circuit region, the first and second gatelines overlapping and contacting the peripheral circuit interconnectpattern; etching back the peripheral circuit interconnect patternconcurrent with etching back the word line pattern and the word lineinterconnect pattern to form a peripheral circuit interconnect having afirst portion with a top surface that is lower than a top surface of theperipheral circuit active regions and second portions that extendvertically from the first portion to contact bottom surfaces ofrespective ones of the second and third gate lines; and forming aninsulating pattern on the first portion of the peripheral circuitinterconnect concurrent with forming the insulating pattern on theburied word line and the first portion of the word line interconnect.20. The method of claim 12, wherein the buried word line extends along aline across the cell region, and wherein the first portion of the wordline interconnect is laterally offset with respect to the line. 21.-44.(canceled)